1. Field of the Invention
The present invention relates to a semiconductor device, a manufacturing method thereof and a method of forming a resist pattern used therein. More particularly, the present invention relates to a semiconductor device having a conducting material film formed in a trench, a manufacturing method thereof and a method of forming a resist pattern used therein.
2. Description of the Background Art
In the field of a DRAM (Dynamic Random Access Memory), which is conventionally known as one type of the semiconductor device, efforts have been made to increase capacity and miniaturize the device. Along with these efforts and achievements, to secure a capacity necessary for a capacitor cell, which is an element of a DRAM, within a limited area of a semiconductor substrate, three-dimensional cells such as a trench type cell or a stacked type cell have been developed. Among the stacked capacitor cells, those with vertically long shape such as a cylindrical type cell or a thick film type cell are mainly used.
FIGS. 17-19 show partial sectional views of a cylindrical stacked capacitor cell, on which the present invention is based and which is referenced for describing the manufacturing process of a lower electrode of a capacitor. With reference to FIGS. 17-19, the manufacturing process of the capacitor lower electrode of the cylindrical stacked capacitor cell will be described.
As shown in FIG. 17, a first interlayer insulation film 115 is formed on a semiconductor substrate (not shown). Openings 116a and 116b are formed in first interlayer insulation film 115. Plugs 117a and 117b are formed respectively in openings 116a and 116b for electrically connecting the capacitor lower electrode and a conducting region in a main surface of the semiconductor substrate. A second interlayer insulation film 123 is formed on first interlayer insulation film 115. Trenches 130a and 130b are formed in second interlayer insulation film 123 in regions above plugs 117a and 117b. Polycrystalline silicon film 119 is formed on second interlayer insulation film 123 as well as in trenchs 130a and 130b. An HSG (Hemi Spherical Grained) polycrystalline silicon film 120 having a resist 127 formed thereon is formed on polycrystalline silicon film 119. Here, HSG polysilicon film means a polysilicon film having roughened surface, and to roughen (roughening) refers to a process of generating hemispherical grains by growing crystal grains.
With etch back of resist 127 using Reactive Ion Etching (hereinafter referred to as RIE), portions 127a and 127b of resist are left in trenches 130a and 130b as shown in FIG. 18 while resist 127 (see FIG. 17) is removed in other regions. Here, the level difference L1 between an upper surface of HSG polycrystalline silicon film 120 on second interlayer insulation film 123 and an upper surfaces of resists 127a and 127b is called recess length. As will be described hereinafter, as portions 127a and 127b of resist are used as masks for removing polycrystalline silicon film 119 and HSG polycrystalline silicon film 120 on second interlayer insulation film 123, the recess length L1 must be controlled with a high precision. If the recess length L1 is too small and the upper surfaces of resist portions 127a and 127b are higher than the upper surface of second interlayer insulation film 123, problems arise. For example, upon etching for removing polycrystalline silicon film 119 and HSG polycrystalline silicon film 120 on the upper surface of second interlayer insulation film 123, etching residue may be produced.
Then using resist portions 127a and 127b as masks, polycrystalline silicon film 119 and HSG polycrystalline silicon film 120 on the upper surface of second interlayer insulation film 123 are etched and removed. Thus a capacitor lower electrode of polycrystalline silicon film 119a and HSG polycrystalline silicon film 120a is formed in trench 130a and a capacitor lower electrode of polycrystalline silicon film 119b and HSG polycrystalline silicon film 120b is formed in trench 130b as shown in FIG. 19.
Then resist portions 127a and 127b are removed and a dielectric film, a capacitor upper electrode and so on are formed on the capacitor lower electrode. The cylindrical stacked capacitor cell is thus formed.
The process shown in FIGS. 17-19 has a following problem. When the resist is etched back by RIE to leave resist portions 127a and 127b only in trenches 130a and 130b as shown in FIG. 18, an oxide film or the like is sometimes partially formed on the surface of HSG polycrystalline silicon film 120 on the upper surface of second interlayer insulation film 123. The oxide film thus formed through RIE serves as a mask upon etching of polycrystalline silicon film 119 and HSG polycrystalline silicon film 120 for isolating the capacitor lower electrode trench by trench. Therefore polycrystalline silicon film 119 or HSG polycrystalline silicon film 120 is sometimes partially left on the upper surface of second interlayer insulation film 123.
When polycrystalline silicon film 119 or the like is left on the upper surface of second interlayer insulation film 123, the capacitor lower electrode is not sufficiently isolated, and whereby a problem such as short circuit of the capacitor lower electrode is caused. As a result, operation failure and reliability degradation of the DRAM occur.
Alternatively, CMP (Chemical Mechanical Polishing) can be used for removing resist 127 (see FIG. 17) in the region outside trenches 130a and 130b for leaving resist portions 127a and 127b in trenches 130a and 130b. In this case, however, slurry used in CMP is left in the area such as an inner area of trenches 130a and 130b, and adversely affects the subsequent process steps. The slurry thus left in trenches 130a and 130b also causes operation failure and reliability degradation of the semiconductor device such as a DRAM.